Backend Mastery Roadmap
CPU Fundamentals
CPU architecture — registers, ALU, control unit, instruction pipeline
Instruction execution cycle — fetch, decode, execute, writeback
Pipeline hazards — data hazards, control hazards, structural hazards
Branch prediction — why mispredictions are expensive (pipeline flush cost)
Out-of-order execution — how CPUs reorder instructions for performance
Speculative execution — what it is, Spectre/Meltdown as consequences
SIMD instructions — vectorized operations, why databases and media use them
Hyper-threading — two logical cores per physical core, shared cache implications
Memory Hierarchy
Cache hierarchy — L1 (~4 cycles), L2 (~12 cycles), L3 (~40 cycles), RAM (~200 cycles)
Cache lines — 64 bytes, why reading one byte loads 64 bytes from memory
Spatial locality — accessing nearby memory is fast (arrays beat linked lists)
Temporal locality — recently accessed data likely accessed again soon
Cache associativity — direct-mapped vs set-associative vs fully associative
False sharing — two threads modifying different variables on the same cache line
Memory latency numbers — cache hit ~1ns, RAM ~100ns, SSD ~100µs, HDD ~10ms
NUMA — Non-Uniform Memory Access, CPU socket affinity in servers
Build
Benchmark sequential vs random array access — quantify cache miss penalty
Demonstrate false sharing: two threads updating adjacent fields vs padded fields
Matrix multiply: row-major vs column-major traversal — measure the difference
Track your progress through all 22 phases